The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jan. 03, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yuji Kayashima, Tokyo, JP;

Tomohisa Sekiguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 24/04 (2013.01); H01L 24/13 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13024 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.


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