The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jan. 31, 2018
Applicant:

Rohm Co., Ltd., Kyoto-shi, Kyoto, JP;

Inventors:

Yuichi Nakao, Kyoto, JP;

Yasuhiro Fuwa, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 21/52 (2006.01); H01L 25/16 (2006.01); H01L 21/56 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/13 (2013.01); H01L 23/147 (2013.01); H01L 23/3121 (2013.01); H01L 23/49827 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/165 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1088 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15156 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15333 (2013.01);
Abstract

A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.


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