Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming

Abstract

A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.