The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Sep. 09, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, Sichuan, CN;

Inventors:

Yuan Wu, Beijing, CN;

Fucheng Yang, Beijing, CN;

Bin Ji, Beijing, CN;

Luxia Jiang, Beijing, CN;

Zheng Wang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3291 (2016.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); G09G 2310/0297 (2013.01); G09G 2320/043 (2013.01); G09G 2320/045 (2013.01);
Abstract

A pixel circuit, a driving method, and array substrate, the pixel circuit includes a plurality of sub-pixel units each of which includes an input sub-circuit, a driving sub-circuit, a light emitting control sub-circuit, and a level maintaining sub-circuit; the input sub-circuit is connected to a data line; the driving sub-circuit outputs a driving current to the light emitting control sub-circuit via a second node under control of a first node; the light emitting control sub-circuit drives a light emitting element to emit light according to a received driving current under control of a light emitting control line; and the level maintaining sub-circuit is connected between the first node and a first voltage terminal to maintain a level at the first node.


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