The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Apr. 13, 2016
Applicant:

Huazhong University of Science and Technology, Wuhan, CN;

Inventors:

Tianxu Zhang, Wuhan, CN;

Xuan Hou, Wuhan, CN;

Chuan Zhang, Wuhan, CN;

Li Liu, Wuhan, CN;

Quan Chen, Wuhan, CN;

Ao Zhong, Wuhan, CN;

Mingxing Xu, Wuhan, CN;

Yutian Zhou, Wuhan, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 5/00 (2006.01); G06T 5/10 (2006.01); G06T 7/73 (2017.01);
U.S. Cl.
CPC ...
G06T 5/002 (2013.01); G06T 5/001 (2013.01); G06T 5/009 (2013.01); G06T 5/10 (2013.01); G06T 7/73 (2017.01); G06T 2207/10048 (2013.01); G06T 2207/20056 (2013.01);
Abstract

An aerodynamic optical effect correction and identification integrated real-time processing system, comprising an FPGA module, a multi-core main processor DSP, a plurality of auxiliary processors ASICs and an infrared image non-uniformity correction system-on-chip (SoC). By means of the system, full-image thermal radiation correction, denoising, transmission effect correction and target detection processes of an aerodynamic optical effect degradation image are achieved. Correspondingly, provided is the corresponding method. The system effectively solves the problem of aerodynamic optical effect and the problem of the requirement for a short detection time interval of the processor in an aircraft flying at a high speed; due to the adoption of the independently researched and developed ASIC, the real-time property of the whole system is greatly improved; all tasks are rationally distributed and a multi-core parallel mode is adopted, so the image processing time is greatly shortened; and meanwhile, the FPGA module connects all units to form a closed-loop system, so that the system stability is further improved.


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