Switching-activity-based selection of low-power sequential circuitry

Abstract

Techniques are disclosed relating to reducing dynamic power consumption in integrated circuits. In some embodiments, simulation is performed at one or more stages of a circuit design to identify portions of the circuit with relatively high average clock switching activity, based on an amount of clock gating during the simulation by one or more clock gaters. In some embodiments, sequential circuit elements in the identified portions are specified as candidates for implementation using low-power sequential circuitry. Examples of low-power sequential circuitry include multibit flip flops and flip flops with low clock pin input capacitance. The disclosed techniques may allow automated design tools to significantly reduce dynamic power consumption while still meeting other design parameters such as timing constraints.