The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Mar. 07, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Hae Chan Park, Gyeonggi-do, KR;

Sung Cheoul Kim, Gyeonggi-do, KR;

Tae Ho Kim, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 13/40 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/06 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G11C 11/005 (2013.01); G11C 11/5607 (2013.01); G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); G11C 16/06 (2013.01); G06F 2212/451 (2013.01); G11C 2211/5641 (2013.01); G11C 2211/5642 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.


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