The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

May. 16, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Javid Jaffari, San Diego, CA (US);

Amin Ansari, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3296 (2019.01); G06F 1/08 (2006.01); G06F 1/28 (2006.01); G06F 1/30 (2006.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/08 (2013.01); G06F 1/28 (2013.01); G06F 1/305 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); Y02D 10/126 (2018.01);
Abstract

Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.


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