The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jun. 19, 2018
Applicant:

Corning Optical Communications Llc, Hickory, NC (US);

Inventors:

Wojciech Piotr Giziewicz, Berlin, DE;

James Phillip Luther, Hickory, NC (US);

Andreas Matiss, Berlin, DE;

Jerald Lee Overcash, China Grove, NC (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); G02B 6/38 (2006.01); G02B 6/30 (2006.01);
U.S. Cl.
CPC ...
G02B 6/423 (2013.01); G02B 6/30 (2013.01); G02B 6/3883 (2013.01); G02B 6/3885 (2013.01); G02B 6/3897 (2013.01); G02B 6/428 (2013.01); G02B 6/4228 (2013.01); G02B 6/4231 (2013.01); G02B 6/4232 (2013.01); G02B 6/4284 (2013.01); G02B 6/4292 (2013.01); G02B 6/4238 (2013.01); G02B 6/4239 (2013.01);
Abstract

Optical ports providing passive alignment connectivity are disclosed. In one embodiment, an optical port includes a substrate having a surface, a photonic silicon chip, a connector body, and a plurality of spacer elements. The photonic silicon chip includes an electrical coupling surface, an upper surface and an optical coupling surface. The optical coupling surface is positioned between the electrical coupling surface and the upper surface. The photonic silicon chip further includes at least one waveguide terminating at the optical coupling surface, and a chip engagement feature disposed on the upper surface. The connector body includes a first alignment feature, a second alignment feature, a mounting surface, and a connector engagement feature at the mounting surface. The connector engagement feature mates with the chip engagement feature. The plurality of spacer elements is disposed between the electrical coupling surface of the photonic silicon chip and the surface of the substrate.


Find Patent Forward Citations

Loading…