The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2019
Filed:
Apr. 16, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G01R 31/3185 (2006.01); G01R 31/3193 (2006.01); G06F 11/267 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31921 (2013.01); G01R 31/3193 (2013.01); G01R 31/31922 (2013.01); G01R 31/318508 (2013.01); G01R 31/318516 (2013.01); G01R 31/318547 (2013.01); G01R 31/318594 (2013.01); G06F 11/267 (2013.01);
Abstract
A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.