The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Nov. 15, 2016
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Da In Im, Icheon-si, KR;

Young Suk Seo, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/222 (2013.01);
Abstract

A delay control device and method are disclosed, which relate to a technology for compensating for a delay difference of a delay locked loop (DLL). The delay control device may include a delay locked loop (DLL) configured to adjust a delay time of a delay line, and compensate for a delay time of a replica delay circuit based on a calibration signal. The delay control device may include a real clock path delay circuit configured to delay an output of the delay locked loop (DLL. The delay control device may include a control signal generator configured to generate the calibration signal in consideration of a difference between the delay time of the replica delay circuit and the delay time of the real clock path delay circuit.


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