The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Feb. 24, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Atsushi Motozawa, Tokyo, JP;

Yoshitaka Hirai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03L 7/087 (2006.01); H03K 19/0175 (2006.01); H02M 3/07 (2006.01); H03L 7/18 (2006.01); H03M 1/74 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); H02M 3/07 (2013.01); H03K 19/017509 (2013.01); H03L 7/087 (2013.01); H03L 7/099 (2013.01); H03L 7/0991 (2013.01); H03L 7/18 (2013.01); H03M 1/742 (2013.01);
Abstract

An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional pathis provided in a first power supply systemand outputs analog proportional signal AP according to a detection signal DET. An integral pathis provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driveris provided in the first power supply systemand outputs control current ICCO according to the AP and the AI. A CCOis provided in the second power supply systemand outputs an output signal Fout according to the ICCO. A phase frequency detectoris provided in the second power supply systemand configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.


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