The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jul. 09, 2018
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Ravindranath D. Shrivastava, San Diego, CA (US);

Raul Inocencio Alidio, Carlsbad, CA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/24 (2006.01); H03G 1/00 (2006.01); H01F 38/14 (2006.01);
U.S. Cl.
CPC ...
H03H 11/245 (2013.01); H01F 38/14 (2013.01); H03G 1/007 (2013.01); H03G 1/0088 (2013.01);
Abstract

A method and apparatus for adjusting the slope of insertion loss of digital step attenuator (DSA). The DSA is implemented on an integrated circuit. The DSA has two series inductances that are introduced between the input of DSA cell and a resistor in the cell, and the output of DSA cell and another resistor in the cell. In one embodiment, adjustment in the value of the series inductances is as achieved by altering the locations of the input port and the output ports. In another embodiment, adjustment in the value of the inductances is achieved by tailoring the length and width of the conductor trace used to connect the input and output ports to the series resistors. The adjustment in the values of the inductances provides a means by which the roll-off of the insertion loss as a function of frequency in the attenuation state can be controlled.


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