The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Oct. 09, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Nikolay Ilkov, Munich, DE;

Andreas Baenisch, Munich, DE;

Peter Pfann, Munich, DE;

Hans-Dieter Wohlmuth, Munich, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03G 3/30 (2006.01); H03F 1/02 (2006.01); H03F 1/22 (2006.01); H03F 1/56 (2006.01); H03F 3/193 (2006.01); H03F 3/45 (2006.01); H03B 5/12 (2006.01);
U.S. Cl.
CPC ...
H03G 3/3036 (2013.01); H03B 5/1212 (2013.01); H03F 1/0205 (2013.01); H03F 1/223 (2013.01); H03F 1/565 (2013.01); H03F 3/193 (2013.01); H03F 3/45475 (2013.01); H03F 2200/171 (2013.01); H03F 2200/18 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01); H03F 2200/456 (2013.01); H03F 2200/534 (2013.01); H03F 2200/541 (2013.01); H03F 2200/555 (2013.01);
Abstract

In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.


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