The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

May. 27, 2017
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Mian Zeng, Guangdong, CN;

Xiaodi Liu, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1288 (2013.01); H01L 21/762 (2013.01); H01L 29/0649 (2013.01); H01L 29/42384 (2013.01); H01L 29/786 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present disclosure relates to a thin film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method includes adopting a shading metal layer to form the bottom gate electrode, depositing a buffer layer on the substrate having the bottom gate electrode, applying a patterned process on the buffer layer to reduce the thickness of the buffer layer on the bottom gate electrode, applying the patterned process on the semiconductor layer to form the semiconductor pattern corresponding to the bottom gate electrode within the thin area of the buffer layer. The present disclosure may reduce a thickness of the buffer layer corresponding to the bottom gate electrode, so as to improve the whole performance of the array substrate caused by the bottom gate electrode.


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