The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jun. 14, 2017
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Chen-Liang Ma, Taoyuan, TW;

Zih-Song Wang, Nantou County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11529 (2017.01); H01L 27/1157 (2017.01); G11C 16/04 (2006.01); H01L 27/11524 (2017.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11529 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/3418 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01);
Abstract

A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.


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