The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jul. 01, 2016
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventor:

Paul Fest, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/033 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/28141 (2013.01); H01L 21/823437 (2013.01); H01L 21/823828 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 21/0337 (2013.01); H01L 21/2815 (2013.01); H01L 21/76816 (2013.01); H01L 29/66553 (2013.01);
Abstract

A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.


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