The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Sep. 06, 2016
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Seung-Hwan Song, San Jose, CA (US);

Viacheslav Anatolyevich Dubeyko, San Jose, CA (US);

Zvonimir Z. Bandic, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 16/10 (2006.01); G06F 11/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); H03M 13/29 (2006.01); G11C 7/14 (2006.01); G11C 11/56 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G06F 11/1068 (2013.01); G11C 7/14 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); G11C 2029/0411 (2013.01);
Abstract

NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.


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