The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Jul. 12, 2017
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Hidetoshi Matsumura, Cupertino, CA (US);

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 15/80 (2006.01); G06F 21/34 (2013.01); G06F 15/78 (2006.01); G06F 21/57 (2013.01); G06F 21/76 (2013.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5054 (2013.01); G06F 15/7867 (2013.01); G06F 15/7871 (2013.01); G06F 15/8007 (2013.01); G06F 21/34 (2013.01); G06F 21/57 (2013.01); G06F 21/76 (2013.01); H04L 9/14 (2013.01); H04L 9/32 (2013.01);
Abstract

A PLD control program causes a computer to execute process including: outputting a configuration request for configuring a logic circuit in any of a plurality of areas where logic circuits are enabled to be reconfigured in a programmable logic device (hereinafter referred to as a PLD); and selecting, when a total size or number of a plurality of first logic circuits already configured in the plurality of areas and a second logic circuit newly configured in accordance with the configuration request exceeds a size or a number of logic circuits that are enabled to be configured in the plurality of areas, a logic circuit to be replaced with the second logic circuit, as a replacement target, from among the plurality of first logic circuits, based on a save and restore time needed to save and restore state data in the first logic circuits.


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