The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

May. 11, 2017
Applicant:

New York University, New York, NY (US);

Inventors:

Ramesh Karri, New York, NY (US);

Jerry Backer, Rosedale, NY (US);

David Hely, Guilherand-Granges, FR;

Assignee:

New York University, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/55 (2013.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 21/554 (2013.01); G06F 21/79 (2013.01); G06F 2221/034 (2013.01);
Abstract

An exemplary system for wrapping an intellectual property core (IP) bus master(s), can include, for example, a plurality of IP cores associated with the IP core bus master(s), and a wrapper module connected to a serial input of the IP core bus master(s) and a serial output of the IP core bus master(s), where the wrapper module can be configured to capture and shift a plurality of values of a system bus for a plurality of bus transfers associated with the IP core bus master(s) and the IP cores. The wrapper module can be further configured to modify a wrapper control logic and a wrapper boundary register of the IP core bus master(s). A plurality of terminals can be included, which can be coupled to the IP core bus master(s), and a plurality of wrapper cells can be included, which can be associated with the plurality of terminals.


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