The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Apr. 14, 2017
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Adrian Michaud, Carlisle, MA (US);

Kenneth J. Taylor, Franklin, MA (US);

Randall Shain, Wrentham, MA (US);

Stephen Wing-Kin Au, Norwood, MA (US);

Junping Zhao, Beijing, CN;

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 12/1009 (2013.01); G06F 2212/6026 (2013.01); G06F 2212/657 (2013.01);
Abstract

Systems, methods, and articles of manufacture comprising processor-readable storage media are provided to implement read-ahead memory operations using learned memory access patterns for memory management systems. For example, a method for managing memory includes receiving a request from requestor (e.g., an active process) to perform a memory access operation, which includes a requested memory address. A determination is made as to whether a data block (e.g., page) associated with the requested memory address resides in a cache memory. When the data block associated with the requested memory address is not in the cache memory, a memory read-ahead process is performed which includes identifying a learned memory access pattern associated with the requestor, wherein the learned memory access pattern includes a plurality of data blocks starting with the data block associated with the requested memory address, and prefetching the plurality of data blocks associated with the learned memory access pattern into the cache memory.


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