The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Apr. 24, 2017
Applicant:

Empire Technology Development Llc, Wilmington, DE (US);

Inventor:

Yan Solihin, Raleigh, NC (US);

Assignee:

Empire Technology Development, LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 12/0806 (2016.01); G06F 12/0875 (2016.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5033 (2013.01); G06F 9/4881 (2013.01); G06F 11/34 (2013.01); G06F 12/0806 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0875 (2013.01); G06F 2201/885 (2013.01); G06F 2209/5018 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/62 (2013.01);
Abstract

Methods and systems to assign threads in a multi-core processor are disclosed. A method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.


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