The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2019
Filed:
Dec. 27, 2012
Nvidia Corporation, Santa Clara, CA (US);
Gerald F. Luiz, Los Gatos, CA (US);
Philip Alexander Cuadra, San Francisco, CA (US);
Luke Durant, Santa Clara, CA (US);
Shirish Gadre, Fremont, CA (US);
Robert Ohannessian, Austin, TX (US);
Lacky V. Shah, Los Altos Hills, CA (US);
Nicholas Wang, Saratoga, CA (US);
Arthur Danskin, San Jose, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.