The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Dec. 30, 2016
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Jake Bear, Lakeside, CA (US);

Dillip K. Dash, San Diego, CA (US);

Majid Nemati Anaraki, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0673 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); H03M 13/1117 (2013.01); H03M 13/6516 (2013.01);
Abstract

The subject technology provides a decoding solution that conserves variable node memory in Low Density Parity Check decoding operations, while supporting multiple choices of code rates. A decoder includes a plurality of variable node memories, with each of the variable node memories having a predetermined memory capacity based on a position of a respective variable node associated with the variable node memory relative to a first variable node in a series of variable nodes. The code rate determines how many of the variable node memories are used, and the size of the data stored in each memory. The capacity of the memories is predetermined so that, as the code rate and number of memories utilized by the decoder increases or decreases, utilization of the memory capacity of each variable node memory is maximized.


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