The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Jan. 22, 2018
Applicant:

Caeleste Cvba, Mechelen, BE;

Inventors:

Gaozhan Cai, Antwerp, BE;

Bart Dierickx, Edegem, BE;

Bert Luyssaert, Ghent, BE;

Peng Gao, Korbeek-Lo, BE;

Assignee:

Caeleste CVBA, Mechelen, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H04N 7/22 (2006.01); G02B 6/12 (2006.01); H01L 27/146 (2006.01); H01L 31/024 (2014.01); H04N 5/369 (2011.01);
U.S. Cl.
CPC ...
H04N 7/22 (2013.01); G02B 6/12002 (2013.01); H01L 27/1464 (2013.01); H01L 27/14623 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 31/024 (2013.01); H04N 5/3696 (2013.01); H04N 5/378 (2013.01); H04N 5/379 (2018.08); G02B 2006/12138 (2013.01); G02B 2006/12142 (2013.01);
Abstract

A stacked image sensor comprises an array of tiles, each comprising a sensor array layer tile comprising a plurality of sensing elements for receiving radiation, one or more electronics layer tiles comprising at least one read-out circuit, connected to at least one subgroup of sensing elements of the sensor array layer tile, a photonics layer tile comprising at least one waveguide and one or more modulators, each connected to the one or more electronics layer tiles. The modulators are adapted for modulating an optical signal travelling within the at least one waveguide. The electronics layer tile comprises at least one driver for driving an optical modulator in the photonics layer tile in accordance with the signals received in each sensing element of the sensor array layer tile. At least one of the layer tiles (sensor array layer, electronics layer and/or photonics layer tiles) is implemented in a single integrated circuit.


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