The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Sep. 01, 2015
Applicant:
Nec Corporation, Minato-ku, Tokyo, JP;
Inventors:
Assignee:
NEC CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); H04L 27/12 (2006.01); G06F 7/544 (2006.01); H04B 1/04 (2006.01); H03M 7/32 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H04L 27/12 (2013.01); G06F 7/544 (2013.01); H03M 3/39 (2013.01); H03M 3/50 (2013.01); H03M 7/3017 (2013.01); H04B 1/04 (2013.01); H03K 19/21 (2013.01); H04B 2001/0408 (2013.01);
Abstract
This ΔΣ modulator is a ΔΣ modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.