The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Nov. 08, 2017
Applicant:

Regents of the University of Minnesota, Minneapolis, MN (US);

Inventors:

Po-Wei Chiu, Minneapolis, MN (US);

Somnath Kundu, Hillsboro, OR (US);

Hyung-il Kim, Woodbury, MN (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04L 7/0041 (2013.01); H04L 7/0087 (2013.01); H04L 25/03031 (2013.01); H04L 2025/03471 (2013.01); H04L 2025/03783 (2013.01);
Abstract

A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.


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