The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Nov. 07, 2018
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Kuo-Sheng Chung, Taipei, TW;

Shih-Hsiung Huang, Miaoli County, TW;

Jie-Fan Lai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/80 (2006.01); H03M 1/10 (2006.01); H03M 1/38 (2006.01); H03M 1/40 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/38 (2013.01); H03M 1/40 (2013.01); H03M 1/462 (2013.01); H03M 1/804 (2013.01);
Abstract

A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.


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