The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

May. 23, 2018
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Tarik Saric, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/093 (2006.01); H03L 7/099 (2006.01); G01S 7/35 (2006.01); H03L 7/095 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); G01S 7/35 (2013.01); H03L 7/095 (2013.01); H03L 7/099 (2013.01);
Abstract

A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage. The voltage source is switchably connected to a node between a first capacitor of the plurality of capacitors and the common voltage line, and is connected to the node during a chirp reset mode defined by the reset pulse such that the voltage at the node is substantially equalized to the initial control voltage.


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