The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Dec. 04, 2015
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Yogesh Jayaraman Sharma, Santa Clara, CA (US);

James Fiorenza, Carlisle, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01); H03K 17/687 (2006.01); H01L 27/088 (2006.01); H01L 29/20 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H01L 27/088 (2013.01); H01L 29/2003 (2013.01); H03F 3/45188 (2013.01); H03F 3/45385 (2013.01); H03F 2200/303 (2013.01); H03F 2200/75 (2013.01); H03F 2203/45036 (2013.01); H03F 2203/45182 (2013.01); H03F 2203/45184 (2013.01); H03F 2203/45188 (2013.01); H03F 2203/45202 (2013.01); H03F 2203/45208 (2013.01); H03F 2203/45224 (2013.01); H03F 2203/45656 (2013.01); H03F 2203/45674 (2013.01); H03F 2203/45676 (2013.01); H03F 2203/45701 (2013.01); H03F 2203/45702 (2013.01); H03F 2203/45722 (2013.01);
Abstract

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.


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