The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Mar. 09, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Keiichi Sawa, Mie, JP;

Shinji Mori, Mie, JP;

Masayuki Tanaka, Mie, JP;

Kenichiro Toratani, Mie, JP;

Takashi Furuhashi, Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 27/11556 (2017.01); H01L 29/167 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 29/167 (2013.01); H01L 29/4975 (2013.01); H01L 29/66825 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.


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