The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Dec. 31, 2015
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Biju Jacob, Schenectady, NY (US);

Habib Vafi, Brookfield, WI (US);

Brian David Yanoff, Schenectady, NY (US);

Jeffery Jon Shaw, Ballston Lake, NY (US);

Jianjun Guo, Ballston Spa, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/146 (2006.01); G01T 1/20 (2006.01); G01T 1/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14689 (2013.01); G01T 1/2018 (2013.01); G01T 1/247 (2013.01); H01L 27/1469 (2013.01); H01L 27/14636 (2013.01); H01L 27/14658 (2013.01); H01L 27/14661 (2013.01); H01L 27/14663 (2013.01); H01L 27/14625 (2013.01);
Abstract

Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.


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