The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Sep. 06, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tomofumi Zushi, Yokkaichi, JP;

Shinya Naito, Toyota, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 29/0649 (2013.01); H01L 29/1033 (2013.01); H01L 27/11565 (2013.01); H01L 29/1041 (2013.01);
Abstract

According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.


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