The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Oct. 26, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Torsten Groening, Paderborn, DE;

Thomas Nuebel, Warstein, DE;

Reinhold Spanke, Bestwig, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 25/07 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 23/055 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 21/4817 (2013.01); H01L 23/055 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01);
Abstract

A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the substrate, which together with the substrate encloses the one or more power semiconductor dies, a plurality of power terminals attached to the first main face of the substrate at a first end, and extending through the plastic housing at a second end to provide a point of external electrical connection for the one or more power semiconductor dies, a potting compound embedding the one or more power semiconductor dies, the first main face of the substrate and at least part of the first end of the plurality of power terminals, and an insulative coating applied only to parts of the plurality of power terminals disposed inside the plastic housing and in contact with just air. A corresponding method of manufacture also is provided.


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