The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Aug. 28, 2015
Applicant:

University of Virginia, Charlottesville, VA (US);

Inventors:

Naser Alijabbari, Elkridge, MD (US);

Robert M. Weikle, II, Crozet, VA (US);

Matthew Bauwens, Chesapeake, VA (US);

Assignee:

UNIVERSITY OF VIRGINIA PATENT FOUNDATION, Charlottesville, VA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/47 (2006.01); H01L 21/18 (2006.01); H01L 29/872 (2006.01); H01L 23/48 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/185 (2013.01); H01L 23/48 (2013.01); H01L 29/20 (2013.01); H01L 29/66212 (2013.01); H01L 29/872 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82 (2013.01); H01L 2224/92244 (2013.01);
Abstract

A quasi-vertical Schottky diode architecture includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin mesa of semiconductor material with epilayers including a bottomside highly-doped layer, a bottomside ohmic contact directly below the anode, and a host substrate onto which the diode material is bonded by a thin adhesive layer. A method of fabricating the diode architecture includes preparation of the semiconductor wafer for processing (including initial etching to expose the highly-doped epilayer, deposition of metals and annealing to form the ohmic contact, application of the adhesive layer to the host substrate, thermal compression bonding of diode wafer and host wafer, with ohmic contact side facing host wafer to form a composite wafer, etching and formation of diode mesas to isolate devices on the host substrate, lithography and formation of topside anode contact and external circuitry on host wafer).


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