The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
May. 26, 2017
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Jin Yong Seong, Seoul, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 11/34 (2006.01); G11C 11/063 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G06F 13/16 (2013.01); G11C 7/1063 (2013.01); G11C 11/063 (2013.01); G11C 11/34 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/22 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3436 (2013.01);
Abstract
Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.