The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Sep. 08, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Satoshi Inoue, Zushi Kanagawa, JP;

Daisuke Arizono, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 7/10 (2006.01); G11C 11/00 (2006.01); G11C 7/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01); G11C 7/10 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/04 (2013.01); G11C 11/00 (2013.01); G11C 2207/2254 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.


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