The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Jan. 27, 2016
Sharp Kabushiki Kaisha, Osaka, JP;
SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;
Abstract
The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL(i−1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer () makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line(i−1)+k via a correction capacitance element (Cc). The inversion delayer () makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.