The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Nov. 30, 2016
Applicant:

Trustees of Boston University, Boston, MA (US);

Inventors:

Ronen Adato, Boston, MA (US);

Ajay Joshi, Lexington, MA (US);

M. Selim Unlu, Newton, MA (US);

Bennett B. Goldberg, Chicago, IL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 21/47 (2006.01); G06T 7/00 (2017.01); G01N 21/956 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06T 7/0006 (2013.01); G01N 21/47 (2013.01); G01N 21/956 (2013.01); G06F 17/5081 (2013.01); G06T 7/0002 (2013.01); G06T 7/0004 (2013.01); G06T 2207/10152 (2013.01); G06T 2207/20021 (2013.01); G06T 2207/20076 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/30148 (2013.01);
Abstract

Optical verification testing of an IC includes obtaining images of the IC by, for each image: (i) illuminating the IC with excitation light, wherein the excitation light corresponds to a respective specific optical excitation of a predefined spectrum of optical excitations (e.g., wavelength spectrum); and (ii) detecting scattered light from the IC in response to the specific optical excitation. For each of a set of sub-regions of the images, the respective sub-region is mapped to at least one of (i) a specific sub-unit of a predefined set of sub-units (e.g., gates) of the IC and (ii) a null result, thereby creating a representation of a detected layout of the IC as an arrangement of the sub-units. The representation can be used to verify that an as-fabricated layout is consistent with an as-designed layout, to detect unauthorized modifications of the IC structure.


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