The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Nov. 29, 2017
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

William L. Walker, Fort Collins, CO (US);

Michael W. Boyer, Bellevue, WA (US);

Yasuko Eckert, Bellevue, WA (US);

Gabriel H. Loh, Bellevue, WA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/0811 (2016.01); G06F 12/128 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0828 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/128 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01);
Abstract

A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.


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