The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2019

Filed:

Apr. 20, 2017
Applicant:

A.u. Vista, Inc., Milpitas, CA (US);

Inventors:

Seok-Lyul Lee, Hsin-chu, TW;

Fang-Chen Luo, Milpitas, CA (US);

Assignee:

A.U. VISTA, INC., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); G02F 1/1339 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1335 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/13394 (2013.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G02F 1/134309 (2013.01); G02F 2001/13606 (2013.01); G02F 2001/13629 (2013.01); G02F 2001/13685 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

A display device using low capacitance bus lines having gate lines and data lines on different substrates. The display device includes a first substrate and a second substrate spaced apart from each other, and a liquid crystal layer is disposed in the cell gap between the first substrate and the second substrate. The data lines of the display device are formed on the first substrate, and the gate lines of the display device are formed on the second substrate. The data lines formed on the first substrate and the gate lines formed on the second substrate are spaced apart by a gate insulator layer and the liquid crystal layer, which increases the gap distance between the data lines and the gate lines. Accordingly, a cross capacitance between each of the data lines and each of the gate lines can be reduced.


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