The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10281525 B1

Date of Patent:

May. 07, 2019

Filed:

Jun. 18, 2015

Semiconductor device and diagnostic test method for both single-point and latent faults using first and second scan tests

Applicant:

Renesas Electric Corporation, Tokyo, JP;

Inventors:

Yoichi Maeda, Kodaira, JP;

Jun Matsushima, Kodaira, JP;

Takayuki Suzuki, Kodaira, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McGinn IP Law Group, PLLC

Primary Examiner:

Cynthia Britt

Int. Cl.

CPC ...

G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01);

U.S. Cl.

CPC ...

G01R 31/3177 (2013.01); G01R 31/31725 (2013.01); G01R 31/318555 (2013.01); G01R 31/318566 (2013.01);

Abstract

A semiconductor device () according to the present invention includes a circuit to be tested () having a scan chain, and a first test control device () and a second test control device () that perform a scan test of the circuit to be tested by using the scan chain. The second test control device () performs a second scan test of the circuit to be tested (), the circuit to be tested () gives the first test control device () an instruction to perform a first scan test after the second scan test is performed, and the first test control device () performs a first scan test of the circuit to be tested () in response to an instruction from the circuit to be tested ().

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