The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

May. 25, 2017
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Toshio Tomonari, Tokyo, JP;

Tsutomu Kobayashi, Tokyo, JP;

Emi Ito, Yamagata, JP;

Yuma Komaya, Tokyo, JP;

Assignee:

TDK CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01F 27/38 (2006.01); H03H 7/42 (2006.01); H01F 27/28 (2006.01); H01F 27/29 (2006.01); H03H 1/00 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); H01F 17/00 (2006.01);
U.S. Cl.
CPC ...
H03H 7/427 (2013.01); H01F 27/2823 (2013.01); H01F 27/29 (2013.01); H01F 27/292 (2013.01); H01F 27/38 (2013.01); H03H 1/00 (2013.01); H05K 1/0233 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H01F 2017/0093 (2013.01); H03H 2001/0085 (2013.01); H03H 2001/0092 (2013.01); H05K 1/0225 (2013.01); H05K 1/0245 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/1006 (2013.01);
Abstract

Disclosed herein is an electronic circuit module that includes a circuit board and a common mode filter mounted on the circuit board. The common mode filter includes first and second terminal electrodes constituting a first pair of terminal electrodes and third and fourth electrodes constituting a second pair of terminal electrodes. The circuit board includes: a first wiring layer having first, second, third, and fourth land patterns connected to the first, second, third, and fourth terminal electrodes, respectively, and first, second, third, and fourth wiring patterns connected to the first, second, third, and fourth land patterns, respectively; and a second wiring layer having a ground pattern that overlaps the first, second, third, and fourth wiring patterns without overlapping the first and second land patterns.


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