The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Aug. 29, 2018
Applicant:

National Chiao Tung University, Hsinchu, TW;

Inventors:

Shih-Hsing Wang, Hsinchu, TW;

Chung-Chih Hung, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/07 (2006.01); H03L 7/06 (2006.01); H03L 7/093 (2006.01); H03K 21/08 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H02M 3/07 (2013.01); H03K 21/08 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01);
Abstract

A charge pump circuit and a phase-locked loop (PLL) system using the same are provided. The charge pump circuit includes an upper current source, a lower current source and a plurality of switches. The switches are turned on or off by an error signal to increase or decrease the control voltage of the voltage-controlled oscillator (VCO) and further control the frequency of the output signal of the VCO. When the reference frequency signal matches with the divided frequency signal from the VCO, the upper current source and the lower current source are bypassed to decrease the voltage across the MOSFET, thereby minimizes the influence of the leakage current on the control voltage of VCO. In this way, the output jitter can be reduced due to smaller magnitude of peak-to-peak voltage on the control voltage of VCO in the PLL system caused by the leakage current of the MOSFET.


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