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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10277112 B1

PDFFull Text
Date of Patent:
Apr. 30, 2019

Filed:

Jun. 16, 2016

Physical topology for a power converter

Applicant:

Tm4 Inc., Boucherville, CA;

Inventors:

Jean-Marc Cyr, Candiac, CA;

Mohammed Amar, Montréal, CA;

Maalainine El Yacoubi, Montréal, CA;

Pascal Fleury, Sainte-Madeleine, CA;

Assignee:

TM4, Inc., Boucherville, QC, CA;

Attorney:

Marshall & Melhorn, LLC

Primary Examiner:

Gary L Laxton

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H02M 1/32 (2007.01); H02M 1/08 (2006.01); H02M 7/00 (2006.01); H02M 7/538 (2007.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H02M 3/158 (2006.01); H02M 7/5387 (2007.01); H02M 3/155 (2006.01); H02M 1/34 (2007.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/32 (2013.01); H01L 23/3675 (2013.01); H01L 23/3735 (2013.01); H01L 23/48 (2013.01); H01L 23/5386 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H02M 1/08 (2013.01); H02M 3/158 (2013.01); H02M 7/003 (2013.01); H02M 7/538 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48139 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/1425 (2013.01); H02M 3/155 (2013.01); H02M 2001/0054 (2013.01); H02M 2001/342 (2013.01); Y02B 70/1491 (2013.01);
Abstract

A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances.

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