The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

May. 30, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chien-Wei Chiu, Beigang Township, Yunlin County, TW;

Hsing-Chao Liu, Jhudong Township, Hsinchu County, TW;

Chun-Fu Liu, Jhudong Township, Hsinchu County, TW;

Ying-Kai Chou, Puzih, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 21/28158 (2013.01); H01L 29/401 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01);
Abstract

A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.


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