The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Aug. 30, 2017
Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;
Yasuyuki Hoshi, Matsumoto, JP;
Masahito Otsuki, Matsumoto, JP;
Shoji Yamada, Matsumoto, JP;
Takashi Shiigi, Matsumoto, JP;
FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;
Abstract
On a front surface of an n-type SiC substrate becoming a drain region, an n-type drift layer, a p-type base layer, and an n-type source layer are sequentially formed by epitaxial growth. In the n-type source layer, the p-type contact region is selectively provided. A trench is provided penetrating the n-type source layer and the p-type base layer in the depth direction and reaching the n-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.