The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Aug. 18, 2017
Applicant:

Hon Hai Precision Industry Co., Ltd., New Taipei, TW;

Inventors:

Hsin-Hua Lin, New Taipei, TW;

Yi-Chun Kao, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/32 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); H01L 21/26513 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1233 (2013.01); H01L 27/1237 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/78675 (2013.01); H01L 27/3262 (2013.01); H01L 29/4908 (2013.01); H01L 29/7869 (2013.01); H01L 29/78621 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.


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