The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Sep. 01, 2016
Applicant:
Toshiba Memory Corporation, Tokyo, JP;
Inventors:
Atsushi Murakoshi, Yokkaichi Mie, JP;
Yasuhito Yoshimizu, Yokkaichi Mie, JP;
Tomofumi Inoue, Yokkaichi Mie, JP;
Tatsuya Kato, Yokkaichi Mie, JP;
Yuta Watanabe, Yokkaichi Mie, JP;
Fumitaka Arai, Yokkaichi Mie, JP;
Assignee:
Toshiba Memory Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11578 (2017.01); H01L 27/11519 (2017.01); H01L 27/11521 (2017.01); H01L 27/11548 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11575 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/42332 (2013.01); H01L 29/42348 (2013.01); H01L 29/42352 (2013.01); H01L 29/66825 (2013.01); H01L 29/7926 (2013.01);
Abstract
According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.