The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Apr. 17, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Mirco Cantoro, Suwon-si, KR;

Yeon Cheol Heo, Suwon-si, KR;

Byoung Gi Kim, Suwon-si, KR;

Chang Min Yoe, Seoul, KR;

Seung Chan Yun, Suwon-si, KR;

Dong Hun Lee, Anyang-si, KR;

Yun Il Lee, Anyang-si, KR;

Hyung Suk Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 23/50 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); B82Y 10/00 (2011.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); B82Y 10/00 (2013.01); H01L 21/823412 (2013.01); H01L 21/823487 (2013.01); H01L 23/50 (2013.01); H01L 29/0676 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66469 (2013.01); H01L 29/775 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H01L 21/823456 (2013.01); H01L 2029/42388 (2013.01);
Abstract

A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.


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